1. Technical Field
The present invention relates to data processing system integrated-circuit chips, and more particularly to programmable logic devices.
2. Background Art
Programmable logic devices are integrated-circuit chips on which large numbers of logical AND and logical OR circuits are fabricated capable of being interconnected through instructions that can be varied to suit the user's needs. Depending upon the manufacturer, these devices may be referred to as a Programmable Logic Array (PLA.TM.), a Programmable Array Logic (PAL) or a Programmable Logic device (PLD). PLDs devices are in the 300- to 500-gate density. The 22V10 is a PLD manufactured by Intel, AMD, and other companies.
Recently, a family of devices called Field Programmable Gate Arrays with a density of 5,000-10,000 gates have been developed. The lower the density, the faster the device can operate; that is, a faster Time Propagation Delay (TPD) through the device. As the density of the devices increases, however, the TPD becomes larger and larger for a given technology.
It is desirable to have a device that keeps the best features of the smaller devices, i.e., the predictability, the high performance, and the lower cost while approaching the density and the richness of features of higher-end devices. Therefore, in between the high-density, slower devices and the lower density, faster devices a family of devices called Complex PLDs have been developed, which are basically a number of small PLDs in one package. A complex PLD known as the Intel iFX780.TM. has eight blocks, each similar to a small PLD, all connected to a global interconnect matrix so that a large number of I/O signals are available on a bus. Each of the eight blocks is similar to a conventional PLD. Each has a fan-in of 24 and a fan-out of 10, with programmable features. Each of the eight blocks takes from the matrix the signals that it needs and can produce up to 10 outputs that are made available at device pins. This results in a high-density package pin count of up to 132 pins.
In many logic design applications using a complex PLD, a comparison of two words having a large number of bits is necessary, such as match a fetch address with the contents of a cache directory. The speed at which this comparison is performed is critical, since the purpose of a cache is to improve memory access response time. Too slow a time propagation delay through the compare circuit would defeat this purpose.
It is therefore an object of the present invention to provide a high-speed wide compare logic in a programmable logic device.